The present embodiments relate to Reed-Solomon decoding, and to circuitry for performing such decoding, particularly on an integrated circuit.
Many modern applications encode data prior to transmission of the data on a network using error-correcting codes such as Reed-Solomon codes. Such codes are capable of providing powerful error correction capability. For example, a Reed-Solomon code of length n and including n−k check symbols may detect any combination of up to 2t=n−k erroneous symbols and correct any combination of up to t symbols.
Reed-Solomon decoding is an important component of RAID (Redundant Array of Independent Disks) storage systems such as RAID 6 that uses dual parity. Conventionally, full Reed-Solomon decoding schemes include both error and erasure capabilities. As an error code, the decoder has to first identify the error location and can then correct up to t symbols as described above. As an erasure code, the decode is provided know error location(s) and can correct up to 2t known erasures. Alternatively, it can detect and correct combinations of errors and erasures. The full Reed-Solomon decoding works but is fairly expensive.
Moreover, increasing communications, storage, and processing demands require ever more efficient error correction including Reed-Solomon forward error correction (FEC). Consequently, it is desirable to provide improved mechanisms for implementing error correction.